XCVC1902-2LLEVIVA Low Latency Ethernet Ports Field Programmable Gate Array

Integrated Circuit Chip XCVC1902-2LLEVIVA Low Latency Ethernet Ports Field Programmable Gate Array

Product Description Of XCVC1902-2LLEVIVA

XCVC1902-2LLEVIVA also possible to reconfigure portions of the PL using Dynamic Function eXchange (DFX). A new device image for a portion of the PL can be loaded from the processing system, through the primary or secondary boot interfaces.

Specification Of XCVC1902-2LLEVIVA

Features Of XCVC1902-2LLEVIVA

• The frequency of the injected sinusoidal jitter is 10 MHz.

• Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE)

• The highest supported line rate when using the RPLL to drive the datapath is 12.5 Gb/s.

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